The present invention relates to a semiconductor memory device, more particularly, to a synchronous semiconductor memory device with an additive latency and a cas latency.
A semiconductor memory device in a system which includes a plurality of semiconductor devices is used for storing data. The semiconductor memory device outputs data stored in a cell corresponding to an address outputted from a data requesting unit, e.g., a central processing unit, or stores data provided from the data requesting unit into the cell.
As an operational speed of a system including a plurality of semiconductor devices has increased and a technology related with a semiconductor integrated circuit has advanced, there has been a demand for increasing data access speed of the semiconductor memory device. In order to access data of semiconductor memory devices at a high speed, a synchronous memory device which receives a system clock and can access data synchronized with transition of the received system clock, is proposed. Nevertheless, the synchronous memory device often cannot meet the data access speed required by the system, and in particular, the data requesting unit included in the system. Accordingly, a double data rate (DDR) synchronous semiconductor memory device is proposed which can access data on every rising edge and falling edge of the system clock.
The DDR synchronous semiconductor memory device should receive or output two data within one cycle of the system clock, since the DDR synchronous semiconductor memory device accesses one data every transition of the system clock. That is, the DDR synchronous semiconductor memory device should output or receive data every time exactly synchronized with the rising edge and falling edge of the system clock.
In order to increase data access speed of the DDR synchronous semiconductor memory device, there are various specifications about timing margins required for receiving a command and accessing data corresponding to the received command. For example, typically, The DDR synchronous semiconductor memory device has specifications such as additive latency (AL) and cas latency (CL). The additive latency is a time margin from when a write or read command is inputted into the DDR synchronous semiconductor memory device, to when an operation corresponding to the inputted write or read command is started at a predetermined time. Also, an address is inputted into the DDR synchronous semiconductor memory device with the inputted write or read command. The cas latency is a time margin from when an operation corresponding to the inputted write or read command is started at a predetermined time, to when data corresponding to the inputted write or read command is inputted into or outputted from the DDR synchronous semiconductor memory device.
Generally, when a write command is carried out in the DDR synchronous semiconductor memory device, in order to harmonize an input time of data inputted into a core area with an input time of a corresponding read command and a corresponding address into the core area, the corresponding write command and the corresponding address are delayed for the additive latency and the cas latency and then, inputted to the core area. Typically, the corresponding write command and the corresponding address are shifted for cycles of an internal clock corresponding to the additive latency and the cas latency.
Alternatively, when a read command is carried out in the DDR synchronous semiconductor memory device, in order to harmonize an output time of data outputted from the core area with an input time of a corresponding read command and a corresponding address into the core area, the corresponding read command and the corresponding address are merely delayed for the additive latency and then, inputted to the core area. Also, the corresponding read command and the corresponding address are shifted for cycles of an internal clock corresponding to the additive latency.
Typically, a data signal stored in a cell of the core area is too small to output it into an external circuit. A data signal stored in a cell corresponding to the read command should be sensed and amplified by a sense amplifier. On a read command, a time corresponding to a cas latency is used for sensing and amplifying a data corresponding to the read command. Hence, the corresponding read command and the corresponding address are not delayed by the cas latency and only delayed by the additive latency into the core area.
FIG. 1 shows a block diagram of a conventional semiconductor memory device. The conventional semiconductor memory device includes a command processing circuit and an address transfer circuit. The command processing circuit includes a command buffer 114, a command decoder 116, a read command AL shifting unit 118, a write command shifting unit 120 and a write address controller 122. The address transfer circuit includes an address buffer 102, an address latch 104, an AL shifting unit 106, a CL shifting unit 110, an address shifting clock generating unit 108 and a column line selecting unit 112.
The command buffer 114 receives command signals RASB, CASB, WEB, and CSB to output command signals RAS, CAS, WE, and CS. The command decoder 116 decodes the command signals RAS, CAS, WE, and CS to generate column command signals, e.g., an access command signal IRDWT, a read command signal ERD, and a write command signal EWT. The read command AL shifting unit 118 shifts the read command signal ERD for periods of an internal clock BCK corresponding to an additive latency AL<0:6> to output a shifted read command signal IRDP. The write command shifting unit 120 shifts the write command signal EWT for periods of an internal clock BCK corresponding to the additive latency AL<0:6> and a cas latency CL<2:7>. The write address controller 122 generates an address control signal EWTS in response to the write command signal EWT and the shifted read command signal IRDP.
The address buffer 102 receives an address signal ADD to output an internal address LA. The address latch 104 latches the internal address LA to output a latched address LAI in response to the access command signal IRDWT. The access command signal IRDWT is a control signal activated in response to either the read command signal ERD or the write command signal EWT. The address shifting clock generating unit 108 generates an address shifting clock BCKD and a write address shifting clock BCKDWT using the internal clock BCK in response to the address control signal EWTS. The AL shifting unit 106 shifts the latched address signal LAI for periods of the address shifting clock BCKD corresponding to the additive latency AL<0:6> to output a read address RDLA. The CL shifting unit 110 shifts the read address RDLA for periods of the write address shifting clock BCKDWT corresponding to the cas latency CL<2:7> to output a write address WTLA. The column line selecting unit 112 generates a selecting signal CAI for selecting one or more of column lines, e.g., bit lines with using the read address RDLA or the write address WTLA in response to the shifted read command signal IRDP or the shifted write command signal IWTP.
FIG. 2 shows a waveform diagram representing an operation of the conventional semiconductor memory device in FIG. 1. When processing a write command, at first, the write command signal EWT generated by the command decoder 116 is outputted to the write address controller 122 and the write command shifting unit 120, respectively. The shifted write command signal IWTP is generated by the write command shifting unit 120. The shifted write command signal IWTP is a signal generated by shifting the writing command signal EWT during a predetermined period corresponding to the additive latency AL<0:6> and the cas latency CL<2:7>. The address control signal EWTS generated by the write address controller 122 is outputted to the address shifting clock generating unit 108. Then, the address shifting clock generating unit 108 generates the address shifting clock BCKD and the write address shifting clock BCKDWT. On the other hand, an address signal corresponding to the write command is inputted to the address buffer 102 and the inputted address is inputted to the AL shifting unit 106 through the address latch 104 as a latched address LAI. The inputted address is shifted by the AL shifting unit 106 and the CL shifting unit 110 and the shifted address, i.e., the write address WTLA is inputted into the column line selecting unit 112. One or more of the column lines in a cell area of the semiconductor memory device is selected by the write address WTLA in response to the shifted write command signal IWTP inputted to the column line selecting unit 112. Data corresponding to the write command is stored at cells of the selected column lines.
When processing a read command, at first, the read command signal ERD generated by the command decoder 116 is outputted to the read command AL shifting unit 118. The shifted read command signal IRDP is generated by the read command AL shifting unit 118. Then, the address control signal EWTS inactivated by the shifted read command signal IRDP is inputted into the write address controller 122. The write address shifting clock BCKDWT is disabled by the inactivated address control signal EWTS. On the other hand, an address signal corresponding to the read command is inputted to the address buffer 102 and the inputted address is inputted to the AL shifting unit 106 through the address latch 104 as a latched address LAI. The inputted address is shifted by the AL shifting unit 106 and the shifted address, i.e., the read address RDLA is inputted into the column line selecting unit 112. In that case, the CL shifting unit is disabled. One or more of the column lines in the cell area is selected by the read address RDLA inputted into the column line selecting unit 112 in response to the shift read command signal IRDP Data stored in cells of the selected column lines is outputted into the external circuit as output data corresponding to the read command.
In case that a read command and a write command are continuously inputted and executed, in other words, a read to write command execution, because of the prior command, i.e., the read command, an address corresponding to the following command, i.e., the write command, can not be transferred into the column line selecting unit 112. That is, if the shifted read command signal IRDP corresponding to the read prior command is activated later than the writing command signal EWT corresponding to the following write command, the shifted read command signal IRDP inactivates the address control signal EWTS which is used for generating the write address shifting clock BCKDWT corresponding to the following write command. Thus, as a result, the write address shifting clock BCKDWT is inactivated and the address corresponding to the write command can not transferred to the column line selecting unit 112 because the CL shifting unit 110 is disabled. In detail, that situation is occurred in case that BL/2+2<=AL. The BL means a burst length representing the number of data accessed corresponding to a command. For example, if BL is 4, AL is one of 4, 5, and 6 or if BL is 8, AL is 6.